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| DS2483 single-channel 1-wire master with adjustable timing and sleep mode ????????????????????????????????????????????????????????????????? maxim integrated products 1 general description the DS2483 is an i 2 c-to-1-wire m bridge device that interfaces directly to standard (100khz max) or fast (400khz max) i 2 c masters to perform protocol con - version between the i 2 c master and any downstream 1-wire slave devices. relative to any attached 1-wire slave device, the DS2483 is a 1-wire master. internal, user-adjustable timers relieve the system host processor from generating time-critical 1-wire waveforms, support - ing both standard and overdrive 1-wire communication speeds. in addition, the 1-wire bus can be powered down under software control. the dual-voltage operation allows different operating voltages on the i 2 c and 1-wire side. strong pullup features support 1-wire power deliv - ery to 1-wire devices such as eeproms and sensors. when not in use, the DS2483 can be put in sleep mode where power consumption is minimal. applications printers medical instruments industrial sensors cell phones benefits and features s i 2 c host interface supports 100khz and 400khz i 2 c communication speeds s standard and overdrive 1-wire communication speeds s adjustable 1-wire timing for t rstl , t msp , t w0l , and t rec0 s 1-wire port can be powered down under software control s supports power-saving sleep mode (slpz pin), where the 1-wire port is in high impedance s i 2 c operating voltages: 1.8v 5%, 3.3v 10%, and 5.0v +5/-10% s built-in level translator: 1-wire operating voltage from 1.8v -5% to 5.0v +5%, independent of i 2 c voltage s built-in esd protection level of 8kv human body model (hbm) contact discharge on io pin s -40 n c to +85 n c operating temperature range s 8-pin tdfn and 6-pin sot23 packages typical application circuit 19-6164; rev 0; 12/11 ordering information appears at end of data sheet. 1-wire is a registered trademark of maxim integrated products, inc. *r p = i 2 c pullup resistor (see the pullup resistor r p sizing section for r p sizing) for related parts and recommended products to use with this part, refer to: www.maxim-ic.com/DS2483.related sda v cc scl slpz io r p * 3v 5v 1-wire bus c (i 2 c port) 1-wire device #1 1-wire device #2 1-wire device #n DS2483 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. www.datasheet.co.kr datasheet pdf - http://www..net/
????????????????????????????????????????????????????????????????? maxim integrated products 2 DS2483 single-channel 1-wire master with adjustable timing and sleep mode voltage range on any pin relative to ground ....... -0.5v to +6v maximum current into any pin ........................................... 20ma operating temperature range .......................... -40 n c to +85 n c junction temperature ..................................................... +150 n c storage temperature range ............................ -55 n c to +125 n c lead temperature (soldering, 10s) ................................. +300 n c soldering temperature (reflow) ...................................... +260 n c absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics (t a = -40 n c to +85 n c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units supply voltage v cc 1.71 5.25 v i 2 c voltage (note 2) v ci2c 1.8v 1.71 1.8 1.89 v 3.3v 2.97 3.3 3.63 5v 4.5 5.0 5.25 supply current i cc no communication, v cc = full range 300 f a sleep mode, v cc = 5.25v 4 sleep mode, v cc = 3.6v 3.0 power-on-reset trip point v por v cc = full range 1.0 1.5 v io pin: general data 1-wire input high voltage v ih1 v cc = full range 0.6 o v cc v 1-wire input low voltage v il1 v cc = full range 0.2 o v cc v 1-wire weak pullup resistor r wpu low range 375 500 815 i high range 700 1000 1375 1-wire output low voltage v ol1 i ol = 8ma sink current 0.2 v active pullup on-threshold v iapo v cc = full range 0.6 0.95 1.2 v active pullup on-time (note 3) t apu 1-wire time slot equal to t rec0 f s 1-wire reset standard speed 2.375 2.5 2.625 1-wire reset overdrive speed 0.475 0.5 0.525 active pullup impedance r apu v cc = 1.71v, 4ma load 100 i v cc = 3.0v, 4ma load 60 v cc = 4.5v, 4ma load 40 1-wire output fall time (note 4) t f1 standard, 10pf < c load < 400pf 0.25 1 f s overdrive, 10pf < c load < 400pf 0.05 0.2 io pin: 1-wire timing (note 5) reset low time t rstl standard -5% see table 7 +5% f s overdrive reset high time t rsth standard and overdrive equal to t rstl f s www.datasheet.co.kr datasheet pdf - http://www..net/ ????????????????????????????????????????????????????????????????? maxim integrated products 3 DS2483 single-channel 1-wire master with adjustable timing and sleep mode electrical characteristics ( continued ) (t a = -40 n c to +85 n c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units presence-detect sample time t msp standard -5% see table 7 +5% f s overdrive sampling for short and interrupt t si standard 7.6 8 8.4 f s overdrive 0.71 0.75 0.79 write-one/read low time t w1l standard 7.6 8 8.4 f s overdrive (note 6) 0.71 0.75 0.79 read sample time t msr standard 11.4 12 12.6 f s overdrive 1.66 1.75 1.84 write-zero low time t w0l standard -5% see table 7 +5% f s overdrive write-zero recovery time t rec0 standard and overdrive -5% see table 7 +5% f s 1-wire time slot t slot standard and overdrive equal to t w0l + t rec0 f s slpz pin low-level input voltage v il v cc = full range -0.5 +0.5 v high-level input voltage v ih (note 7) 1.3 v ccact v input leakage current (note 2) i i v ci2c < 1.89v 6 f a v ci2c < 3.63v 15 v ci2c < 5.25v 32 wake-up time from sleep mode t swup (notes 4, 8) 2 ms i 2 c scl and sda pins (note 9) low-level input voltage v il v ci2c = full range -0.5 0.3 o v ci2c v high-level input voltage v ih 0.7 o v ci2c v ci2c + 0.5v v hysteresis of schmitt trigger inputs (note 4) v hys v ci2c > 2.0v 0.05 o v ci2c v v ci2c < 2.0v 0.1 o v ci2c low-level output voltage at 3ma sink current v ol v ci2c > 2.0v 0.4 v v ci2c < 2.0v 0.2 o v ci2c output fall time from v ih(min) to v il(max) with a bus capacitance from 10pf to 400pf t of (note 4) 60 250 ns pulse width of spikes suppressed by input filter t sp 50 ns www.datasheet.co.kr datasheet pdf - http://www..net/ ????????????????????????????????????????????????????????????????? maxim integrated products 4 DS2483 single-channel 1-wire master with adjustable timing and sleep mode note 1: limits are 100% production tested at t a = +25c and/or t a = +85c. limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. typical values are not guaranteed. note 2: the v ci2c voltage is applied at the slpz pin. v ci2c must always be < v cc . the DS2483 measures v ci2c after t swup (wakeup from sleep mode) or after t oscwup (power-on reset). the device reset command does not cause the DS2483 to measure v ci2c . note 3: the active pullup does not apply to the rising edge of a presence pulse outside of a 1-wire reset command or during the recovery after a short on the 1-wire line. note 4: guaranteed design and not production tested. note 5: except for t f1 , all 1-wire timing specifications are derived from the same timing circuit. note 6: although 1-wire slave data sheets specify a t w1l and t rl minimum of 1s, 1-wire slaves will accept the shorter 0.71s t w1l and t rl of the DS2483. note 7: v ccact refers to the v cc level being applied in the application. note 8: i 2 c communication should not take place for the max t oscwup or t swup time following a power-on reset or a wake-up from sleep mode. note 9: all i 2 c timing values are referenced to v ih(min) and v il(max) levels. note 10: the DS2483 does not obstruct the sda and scl lines if slpz is at 0v or if v cc is switched off. note 11: the DS2483 provides a hold time of at least 300ns for the sda signal (referenced to the v ih(min) of the scl signal) to bridge the undefined region of the falling edge of scl. note 12: the maximum t hd:dat must only be met if the device does not stretch the low period (t low ) of the scl signal. note 13: a fast mode i 2 c bus device can be used in a standard mode i 2 c bus system, but the requirement t su:dat r 250ns must then be met. this requirement is met since the DS2483 does not stretch the low period of the scl signal. also the acknowledge timing must meet this setup time (i 2 c bus specification rev. 03, 19 june 2007). note 14: c b = total capacitance of one bus line in pf. the maximum bus capacitance allowable can vary from this value depend - ing on the actual operating voltage and frequency of the application (i 2 c bus specification rev. 03, 19 june 2007). electrical characteristics ( continued ) (t a = -40 n c to +85 n c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units input current with input voltage between 0.1 o v cc(max) and 0.9 o v cc(max) i i (note 10) -10 +10 f a input capacitance c i (note 4) 10 pf scl clock frequency f scl 0 400 khz hold time (repeated) start condition (after this period, the first clock pulse is generated.) t hd:sta 0.6 f s low period of the scl clock t low 1.3 f s high period of the scl clock t high 0.6 f s setup time for a repeated start condition t su:sta 0.6 f s data hold time t hd:dat (notes 11, 12) 0.9 f s data setup time t su:dat (note 13) 250 ns setup time for stop condition t su:sto 0.6 f s bus free time between a stop and start condition t buf 1.3 f s capacitive load for each bus line c b (notes 4, 14) 400 pf oscillator warmup time t oscwup (notes 4, 8) 2 ms www.datasheet.co.kr datasheet pdf - http://www..net/ ????????????????????????????????????????????????????????????????? maxim integrated products 5 DS2483 single-channel 1-wire master with adjustable timing and sleep mode pin configurations pin description pin name function tdfn-ep sot23 1 3 scl i 2 c serial-clock input. must be connected to the i 2 c bus supply voltage through a pullup resistor. 2 2 sda i 2 c serial-data input/output. must be connected to the i 2 c bus supply voltage through a pul - lup resistor. 3 1 slpz power supply for i 2 c port and active-low control input to activate the low-power sleep mode. this pin can be driven directly by a push-pull port or by an open-drain port with a 2.2k i pullup resistor to the i 2 c voltage (v ci2c ) over the entire operating voltage range. 4, 5 n.c. no connection. not internally connected. 6 6 v cc power-supply input 7 5 io input/output driver for 1-wire line 8 4 gnd ground reference ep exposed pad (tdfn only). solder evenly to the boards ground plane for proper operation. refer to application note 3273: exposed pads: a brief introduction for additional information. 1 + 3 4 8 6 5 gnd v cc n.c. 2 7 io scl slpz ep n.c. sda tdfn (2mm x 3mm) top view sot23 top view sda scl 1 slpz 2 3 gnd 3grr rr = revision code 6 v cc 5 i o + 4 DS2483 DS2483 www.datasheet.co.kr datasheet pdf - http://www..net/ ????????????????????????????????????????????????????????????????? maxim integrated products 6 DS2483 single-channel 1-wire master with adjustable timing and sleep mode detailed description the DS2483 is a self-timed 1-wire master that supports advanced 1-wire waveform features including standard and overdrive speeds, active pullup, and strong pullup for power delivery. the active pullup affects rising edges on the 1-wire side. the strong pullup function uses the same pullup transistor as the active pullup, but with a different control algorithm. once supplied with command and data, the input/output controller of the DS2483 per - forms time-critical 1-wire communication functions such as reset/presence-detect cycle, read-byte, write-byte, single bit r/w, and triplet for rom search, without requir - ing interaction with the host processor. the host obtains feedback (completion of a 1-wire function, presence pulse, 1-wire short, search direction taken) through the status register and data through the read data regis - ter. the DS2483 communicates with a host processor through its i 2 c bus interface in standard mode or in fast mode. see figure 1 for a block diagram. device registers the DS2483 has four registers that the i 2 c host can read: device configuration, status, read data, and port configuration. these registers are addressed by a read pointer. the position of the read pointer, i.e., the reg - ister that the host reads in a subsequent read access, is defined by the instruction the DS2483 executed last. to enable certain 1-wire features, the host has read- and write-access to the device configuration and port configuration registers. device configuration register the DS2483 supports four 1-wire features that are enabled or selected through the device configuration register ( table 1 ). these features are as follows: ? active pullup (apu) ? 1-wire power-down (pdn) ? strong pullup (spu) ? 1-wire speed (1ws) apu, spu, and 1ws can be selected in any combination. while apu and 1ws maintain their states, spu returns to its inactive state as soon as the strong pullup has ended. after a device reset (power-up cycle or initiated by the device reset command), the device configuration reg - ister reads 00h. when writing to the device configuration register, the new data is accepted only if the upper nibble (bits 7 to 4) is the ones complement of the lower nibble (bits 3 to 0). when read, the upper nibble is always 0h. figure 1. block diagram table 1. device configuration register bit assignment bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1ws spu pdn apu 1ws spu pdn apu configuration and timing register i 2 c interface controller input/output controller line xcvr t-time osc status register read data register sda io slpz gnd scl v cc DS2483 www.datasheet.co.kr datasheet pdf - http://www..net/ ????????????????????????????????????????????????????????????????? maxim integrated products 7 DS2483 single-channel 1-wire master with adjustable timing and sleep mode active pullup (apu) the apu bit controls whether an active pullup (low impedance transistor) or a passive pullup (r wpu resis - tor) is used to drive a 1-wire line from low to high. when apu = 0, active pullup is disabled (resistor mode). enabling active pullup is generally recommended for best 1-wire bus performance. the active pullup does not apply to the rising edge of a recovery after a short on the 1-wire line. if enabled, a fixed-duration active pullup (typically 2.5 f s standard speed, 0.5 f s overdrive speed) also applies in a reset/presence detect cycle on the rising edges after t rstl and after t pdl . the circuit that controls rising edges operates as follows ( figure 2 ): at t 1 , the pulldown (from DS2483 or 1-wire slave) ends. from this point on the 1-wire bus is pulled high through r wpu internal to the DS2483. v cc and the capacitive load of the 1-wire line determine the slope. in case that active pullup is disabled (apu = 0), the resis - tive pullup continues, as represented by the solid line. with active pullup enabled (apu = 1), and when at t 2 the voltage has reached the v iapo threshold, the DS2483 activates a low-impedance pullup transistor, as repre - sented by the dashed line. the active pullup remains active until the end of the time slot (t 3 ), after which the resistive pullup continues. the shortest duration of the active pullup is t rec0 - (t 2 - t 1 ) in a write-zero time slot and the longest duration is t w0l + t rec0 - t w1l - (t 2 - t 1 ) in a write-one time slot. in a read-data time slot, the active pullup duration is slave dependent. see the strong pullup (spu) section for a way to keep the pullup transis - tor conducting beyond t 3 . 1-wire power down (pdn) the pdn bit is used to remove power from the 1-wire port, e.g., to force a 1-wire slave to perform a power-on reset. pdn can as well be used in conjunction with the sleep mode (see table 2 for details). while pdn is 1, no 1-wire communication is possible. to end the 1-wire power-down state, the pdn bit must be changed to 0. note: when writing to the device configuration register with pdn = 1 to activate the 1-wire power-down mode, make sure that the spu bit is 0. table 2. effects of pdn and slpz figure 2. rising edge pullup as seen at the end of a write-zero time slot pdn = slpz is logic 0 slpz is logic 1 0 ? r wpu is connected. ? io is at v cc , keeping the slaves powered. ? the DS2483 is powered down (sleep mode). ? r wpu is connected. ? io is at v cc , keeping the slaves powered. ? the DS2483 is powered up (normal operation). 1 ? r wpu is disconnected. ? io is at 0v, causing the slaves to lose power. ? the DS2483 is powered down (sleep mode). ? r wpu is disconnected. ? io is at 0v, causing the slaves to lose power. ? the DS2483 is powered up. apu = 0 next time slot apu = 1 v cc 0v 1-wire bus is discharged t 1 t 2 t 3 v iapo v il1max t rec0 www.datasheet.co.kr datasheet pdf - http://www..net/ ????????????????????????????????????????????????????????????????? maxim integrated products 8 DS2483 single-channel 1-wire master with adjustable timing and sleep mode strong pullup (spu) the spu bit is used to activate the strong pullup func - tion prior to a 1-wire write byte or 1-wire single bit command. strong pullup is commonly used with 1-wire eeprom devices when copying scratchpad data to the main memory or when performing a sha computation and with parasitically powered temperature sensors or a/d converters. the respective maxim 1-wire ic data sheets specify the location in the communications proto - col after which the strong pullup should be applied. the spu bit must be set immediately prior to issuing the com - mand that puts the 1-wire device into the state where it needs the extra power. the strong pullup uses the same internal pullup transistor as the active pullup feature. see the r apu parameter in the electrical characteristics to determine whether the voltage drop is low enough to maintain the required 1-wire voltage at a given load cur - rent and 1-wire supply voltage. if spu is 1 and apu is 0, the DS2483 treats the rising edge of the time slot as if the active pullup was activat - ed, but uses v ih1 as the threshold to enable the strong pullup. if spu is 1 and apu is 1, the threshold voltage to enable the strong pullup is v iapo . once enabled, in contrast to the active pullup, the internal pullup transis - tor remains conducting, as shown in figure 3 , until one of three events occurs: the DS2483 receives a com - mand that generates 1-wire communication (the typical case), the spu bit in the device configuration register is written to 0, or the DS2483 receives the device reset command. when the strong pullup ends, the spu bit is automatically reset to 0. using the strong pullup feature does not change the state of the apu bit in the device configuration register. 1-wire speed (1ws) the 1ws bit determines the timing of any 1-wire com - munication generated by the DS2483. all 1-wire slave devices support standard speed (1ws = 0). many 1-wire devices can also communicate at a higher data rate, called overdrive speed. to change from standard to overdrive speed, a 1-wire device needs to receive an overdrive-skip rom or overdrive-match rom com - mand, as explained in the maxim 1-wire ic data sheets. the change in speed occurs immediately after the 1-wire device has received the speed-changing command code. the DS2483 must take part in this speed change to stay synchronized. this is accomplished by writing to the device configuration register with the 1ws bit as 1 immediately after the 1-wire byte command that changes the speed of a 1-wire device. writing to the device configuration register with the 1ws bit as 0, followed by a 1-wire reset command, changes the DS2483 and any 1-wire devices on the active 1-wire line back to standard speed. figure 3. low-impedance pullup timing DS2483 resistive pullup DS2483 pulldown DS2483 strong pullup v cc see text 0v write-zero case write-one case t slot last bit of 1-wire write byte or 1-wire single bit function next time slot or 1-wire reset www.datasheet.co.kr datasheet pdf - http://www..net/ ????????????????????????????????????????????????????????????????? maxim integrated products 9 DS2483 single-channel 1-wire master with adjustable timing and sleep mode status register the read-only status register is the general means for the DS2483 to report bit-type data from the 1-wire side, 1-wire busy status, and its own reset status to the host processor ( table 3 ). all 1-wire communication com - mands and the device reset command position the read pointer at the status register for the host processor to read with minimal protocol overhead. status information is updated during the execution of certain commands only. bit details are given in the following descriptions. 1-wire busy (1wb) the 1wb bit reports to the host processor whether the 1-wire line is busy. during 1-wire communication 1wb is 1; once the command is completed, 1wb returns to its default 0. details on when 1wb changes state and for how long it remains at 1 are found in the function commands section. presence-pulse detect (ppd) the ppd bit is updated with every 1-wire reset com - mand. if the DS2483 detects a presence pulse from a 1-wire device at t msp during the presence-detect cycle, the ppd bit is set to 1. this bit returns to its default 0 if there is no presence pulse or if the 1-wire line is shorted during a subsequent 1-wire reset command. short detected (sd) the sd bit is updated with every 1-wire reset com - mand. if the DS2483 detects a logic 0 on the 1-wire line at t si during the presence-detect cycle, the sd bit is set to 1. this bit returns to its default 0 with a subsequent 1-wire reset command, provided that the short has been removed. if sd is 1, ppd is 0. the DS2483 cannot dis - tinguish between a short and a ds1994 or ds2404 sig - naling a 1-wire interrupt. for this reason, if a ds2404 or ds1994 is used in the application, the interrupt function must be disabled. the interrupt signaling is explained in the respective maxim 1-wire ic data sheets. logic level (ll) the ll bit reports the logic state of the active 1-wire line without initiating any 1-wire communication. the 1-wire line is sampled for this purpose every time the status register is read. the sampling and updating of the ll bit takes place when the host processor has addressed the DS2483 in read mode (during the acknowledge cycle), provided that the read pointer is positioned at the status register. device reset (rst) if the rst bit is 1, the DS2483 has performed an internal reset cycle, either caused by a power-on reset or from executing the device reset command. the rst bit is cleared automatically when the DS2483 executes a write device configuration command to restore the selection of the desired 1-wire features. single bit result (sbr) the sbr bit reports the logic state of the active 1-wire line sampled at t msr of a 1-wire single bit command or the first bit of a 1-wire triplet command. the power-on default of sbr is 0. if the 1-wire single bit command sends a 0 bit, sbr should be 0. with a 1-wire triplet command, sbr could be 0 as well as 1, depending on the response of the 1-wire devices connected. the same result applies to a 1-wire single bit command that sends a 1 bit. triplet second bit (tsb) the tsb bit reports the logic state of the active 1-wire line sampled at t msr of the second bit of a 1-wire triplet command. the power-on default of tsb is 0. this bit is updated only with a 1-wire triplet command and has no function with other commands. branch direction taken (dir) whenever a 1-wire triplet command is executed, this bit reports to the host processor the search direction that was chosen by the third bit of the triplet. the power-on default of dir is 0. this bit is updated only with a 1-wire triplet command and has no function with other com - mands. for additional information, see the description of the 1-wire triplet command and application note 187: 1-wire search algorithm . table 3. status register bit assignment bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dir tsb sbr rst ll sd ppd 1wb www.datasheet.co.kr datasheet pdf - http://www..net/ ???????????????????????????????????????????????????????????????? maxim integrated products 10 DS2483 single-channel 1-wire master with adjustable timing and sleep mode port configuration register the port configuration register allows verifying the set - tings for the 1-wire port ( table 4 ). the adjust 1-wire port command positions the read pointer to the port configuration register for the host processor to read with minimal protocol overhead. when reading the port configuration register, the parameter values are reported in this sequence: parameter 000 (t rstl ) standard speed, overdrive speed parameter 001 (t msp ) standard speed, overdrive speed parameter 010 (t w0l ) standard speed, overdrive speed parameter 011 (t rec0 ) parameter 100 (r wpu ) if one continues reading, the parameter number rolls over to 000 and one receives the same data again. note that the upper 4 bits read from the port configura - tion register are always 0. see table 7 for the conversion between parameter value code and actual parameter value. function commands the DS2483 understands nine function commands that fall into four categories: device control, i 2 c communi - cation, 1-wire setup, and 1-wire communication. the feedback path to the host is controlled by a read pointer, which is set automatically by each function command for the host to efficiently access relevant information. the host processor sends these commands and appli - cable parameters as strings of 1 or 2 bytes using the i 2 c interface. the i 2 c protocol requires that each byte be acknowledged by the receiving party to confirm acceptance or not be acknowledged to indicate an error condition (invalid code or parameter) or to end the com - munication. see the i 2 c interface section for details of the i 2 c protocol including acknowledge. the function commands are as follows: 1) device reset 2) set read pointer 3) write device configuration 4) adjust 1-wire port 5) 1-wire reset 6) 1-wire single bit 7) 1-wire write byte 8) 1-wire read byte 9) 1-wire triplet table 4. port configuration register bit assignment bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 0 val3 val2 val1 val0 bits 3:0 val[3:0] : parameter value code see table 7 for the conversion between binary code and parameter value. www.datasheet.co.kr datasheet pdf - http://www..net/ ???????????????????????????????????????????????????????????????? maxim integrated products 11 DS2483 single-channel 1-wire master with adjustable timing and sleep mode device reset set read pointer table 5. valid read pointer codes command code f0h command parameter none description performs a global reset of device state machine logic. terminates any ongoing 1-wire com - munication. typical use device initialization after power-up; reinitialization (reset) as desired. restriction none (can be executed at any time) error response none command duration maximum 525ns. counted from falling scl edge of the command code acknowledge bit. 1-wire activity ends maximum 262.5ns after the falling scl edge of the command code acknowledge bit. read pointer position status register (for busy polling). status bits affected rst set to 1; 1wb, ppd, sd, sbr, tsb, dir set to 0. device configurations affected 1ws, apu, pdn, spu set to 0. port configurations affected t rstl , t msp , t w0l , t rec0 , and r wpu default values apply. command code e1h command parameter pointer code (see table 5) description sets the read pointer to the specified register. overwrites the read pointer position of any 1-wire communication command in progress. typical use to prepare reading the result from a 1-wire read byte command; random read access of registers. restriction none (can be executed at any time). error response if the pointer code is not valid, the pointer code is not acknowledged and the command is ignored. command duration none. the read pointer is updated on the rising scl edge of the pointer code acknowledge bit. 1-wire activity not affected. read pointer position as specified by the pointer code. status bits affected none device configurations affected none port configurations affected none register code device configuration register c3h status register f0h read data register e1h port configuration register b4h www.datasheet.co.kr datasheet pdf - http://www..net/ ???????????????????????????????????????????????????????????????? maxim integrated products 12 DS2483 single-channel 1-wire master with adjustable timing and sleep mode adjust 1-wire port write device configuration command code c3h command parameter control byte description updates the selected 1-wire port parameter, which affects the 1-wire timing or pullup resis - tor selection. see table 6 for the control byte format. note: upon a power-on reset or after a device reset command, the parameter default values apply. typical use to adapt the 1-wire port to the needs of the application. this can be necessary to accom - modate the slave timing requirements, which are different at lower pullup voltage. restriction 1-wire activity must have ended before this command can be processed. error response command code and data byte are not acknowledged if 1wb = 1 at the time the command code is received and the command is ignored. command duration none. the selected port parameter is updated on the rising scl edge of the control-byte acknowledge bit. 1-wire activity none read pointer position port configuration register (for verification). status bits affected none device configurations affected none port configurations affected as specified by the control byte. command code d2h command parameter configuration byte description writes a new device configuration byte. the new settings take effect immediately. note: when writing to the device configuration register, the new data is accepted only if the upper nibble (bits 7 to 4) is the ones complement of the lower nibble (bits 3 to 0). when read, the upper nibble is always 0h. typical use defining the features for subsequent 1-wire communication. restriction 1-wire activity must have ended before the DS2483 can process this command. error response command code and parameter are not acknowledged if 1wb = 1 at the time the command code is received and the command is ignored. command duration none. the device configuration register is updated on the rising scl edge of the configura - tion-byte acknowledge bit. 1-wire activity none read pointer position device configuration register (to verify write). status bits affected rst set to 0. device configurations affected 1ws, spu, pdn, apu updated. port configurations affected none www.datasheet.co.kr datasheet pdf - http://www..net/ ???????????????????????????????????????????????????????????????? maxim integrated products 13 DS2483 single-channel 1-wire master with adjustable timing and sleep mode table 6. bit allocation in the control byte table 7. conversion between parameter code and typical parameter value note: the power-on default values are bold . bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p2 p1 p0 od val3 val2 val1 val0 bits 7:5 p[2:0]: parameter selection 000: selects t rstl 001: selects t msp 010: selects t w0l 011: selects t rec0 ; the od flag does not apply (dont care) 100: selects r wpu ; the od flag does not apply (dont care) bit 4 od: overdrive control 0: the value provided applies to the standard speed setting 1: the value provided applies to the overdrive speed setting bits 3:0 val[3:0] : parameter value code see table 7 for the conversion between binary code and parameter value. parameter value code parameter 000 t rstl (s) parameter 001 t msp ( s) parameter 010 t w0l (s) parameter 011 t rec0 (s) parameter 100 r wpu ( w ) od = 0 od = 1 od = 0 od = 1 od = 0 od = 1 od = n/a od = n/a 0000 440 44 58 5.5 52 5.0 2.75 500 0001 460 46 58 5.5 54 5.5 2.75 500 0010 480 48 60 6.0 56 6.0 2.75 500 0011 500 50 62 6.5 58 6.5 2.75 500 0100 520 52 64 7.0 60 7.0 2.75 500 0101 540 54 66 7.5 62 7.5 2.75 500 0110 560 56 68 8.0 64 8.0 5.25 1000 0111 580 58 70 8.5 66 8.5 7.75 1000 1000 600 60 72 9.0 68 9.0 10.25 1000 1001 620 62 74 9.5 70 9.5 12.75 1000 1010 640 64 76 10.0 70 10 15.25 1000 1011 660 66 76 10.5 70 10 17.75 1000 1100 680 68 76 11.0 70 10 20.25 1000 1101 700 70 76 11.0 70 10 22.75 1000 1110 720 72 76 11.0 70 10 25.25 1000 1111 740 74 76 11.0 70 10 25.25 1000 www.datasheet.co.kr datasheet pdf - http://www..net/ ???????????????????????????????????????????????????????????????? maxim integrated products 14 DS2483 single-channel 1-wire master with adjustable timing and sleep mode 1-wire reset figure 4. 1-wire reset/presence-detect cycle command code b4h command parameter none description generates a 1-wire reset/presence-detect cycle at the 1-wire line (figure 4). the state of the 1-wire line is sampled at t si and t msp and the result is reported to the host processor through the status register bits ppd and sd. typical use to initiate or end any 1-wire communication sequence. restriction 1-wire activity must have ended before the DS2483 can process this command. error response command code is not acknowledged if 1wb = 1 at the time the command code is received and the command is ignored. command duration 2 o t rstl + maximum 262.5ns, counted from the falling scl edge of the command code acknowledge bit. 1-wire activity begins maximum 262.5ns after the falling scl edge of the command code acknowledge bit. read pointer position status register (for busy polling). status bits affected 1wb (set to 1 for 2 o t rstl ), ppd is updated at t rstl + t msp , sd is updated at t rstl + t si . device configurations affected 1ws and apu apply. port configurations affected t rstl , t msp , t w0l , t rec0 , and r wpu current values apply. pullup (see figure 2) DS2483 pulldown 1-wire slave pulldown v cc v ih1 v il1 0v reset pulse presence/short detect t rstl t si t msp t rsth t f1 presence pulse apu controlled edge www.datasheet.co.kr datasheet pdf - http://www..net/ ???????????????????????????????????????????????????????????????? maxim integrated products 15 DS2483 single-channel 1-wire master with adjustable timing and sleep mode 1-wire single bit table 8. bit allocation in the bit byte x = dont care command code 87h command parameter bit byte description generates a single 1-wire time slot with a bit value v as specified by the bit byte at the 1-wire line (table 8). a v value of 0b generates a write-zero time slot (figure 5); a v value of 1b generates a write-one time slot, which also functions as a read-data time slot (figure 6). in either case, the logic level at the 1-wire line is tested at t msr and sbr is updated. typical use to perform single-bit writes or reads at the 1-wire line when single bit communication is necessary (the exception). restriction 1-wire activity must have ended before the DS2483 can process this command. error response command code and bit byte are not acknowledged if 1wb = 1 at the time the command code is received and the command is ignored. command duration t slot + maximum 262.5ns, counted from the falling scl edge of the first bit (msb) of the bit byte. 1-wire activity begins maximum 262.5ns after the falling scl edge of the msb of the bit byte. read pointer position status register (for busy polling and data reading). status bits affected 1wb (set to 1 for t slot ), sbr is updated at t msr , dir (may change its state). device configurations affected 1ws, apu, spu apply. port configurations affected t rstl , t msp , t w0l , t rec0 , and r wpu current values apply. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v x x x x x x x www.datasheet.co.kr datasheet pdf - http://www..net/ ???????????????????????????????????????????????????????????????? maxim integrated products 16 DS2483 single-channel 1-wire master with adjustable timing and sleep mode figure 6. write-one and read-data time slot figure 5. write-zero time slot pullup (see figure 2) DS2483 pulldown 1-wire slave pulldown v cc v ih1 v il1 0v t slot t w1l t msr t f1 note: depending on its internal state, a 1-wire slave device transmits data to its master (e.g., the DS2483). when responding with a 0, a 1-wire slave starts pulling the line low during t w1l . its internal timing generator determines when this pulldown ends and the voltage starts rising again. when responding with a 1, a 1-wire slave does not hold the line low at all, and the voltage starts rising as soon as t w1l is over. 1-wire device data sheets use the term t rl instead of t w1l to describe a read-data time slot. technically, t rl and t w1l have identical specifications and cannot be distinguished from each other. pullup (see figure 2) DS2483 pulldown v cc v ih1 v il1 0v t slot t r ec0 t wol t msr t f1 www.datasheet.co.kr datasheet pdf - http://www..net/ ???????????????????????????????????????????????????????????????? maxim integrated products 17 DS2483 single-channel 1-wire master with adjustable timing and sleep mode 1-wire write byte 1-wire read byte command code a5h command parameter data byte description writes a single data byte to the 1-wire line. typical use to write commands or data to the 1-wire line. equivalent to executing eight 1-wire single bit commands, but faster due to less i 2 c traffic. restriction 1-wire activity must have ended before the DS2483 can process this command. error response command code and data byte are not acknowledged if 1wb = 1 at the time the command code is received and the command is ignored. command duration 8 x t slot + maximum 262.5ns, counted from falling edge of the last bit (lsb) of the data byte. 1-wire activity begins maximum 262.5ns after falling scl edge of the lsb of the data byte (i.e., before the data-byte acknowledge). note: the bit order on the i 2 c bus and the 1-wire line is different (1-wire: lsb first; i 2 c: msb first). therefore, 1-wire activity cannot begin before the DS2483 has received the full data byte. read pointer position status register (for busy polling). status bits affected 1wb (set to 1 for 8 x t slot ). device configurations affected 1ws, spu, apu apply. port configurations affected t rstl , t msp , t w0l , t rec0 , and r wpu current values apply. command code 96h command parameter none description generates eight read-data time slots on the 1-wire line and stores result in the read data register. typical use to read data from the 1-wire line. equivalent to executing eight 1-wire single bit commands with v = 1 (write-one time slot), but faster due to less i 2 c traffic. restriction 1-wire activity must have ended before the DS2483 can process this command. error response command code is not acknowledged if 1wb = 1 at the time the command code is received and the command is ignored. command duration 8 x t slot + maximum 262.5ns, counted from the falling scl edge of the command code acknowledge bit. 1-wire activity begins maximum 262.5ns after the falling scl edge of the command code acknowledge bit. read pointer position status register (for busy polling). note: to read the data byte received from the 1-wire line, issue the set read pointer command and select the read data register. then access the DS2483 in read mode. status bits affected 1wb (set to 1 for 8 x t slot ). device configurations affected 1ws, apu apply. port configurations affected t rstl , t msp , t w0l , t rec0 , and r wpu current values apply. www.datasheet.co.kr datasheet pdf - http://www..net/ ???????????????????????????????????????????????????????????????? maxim integrated products 18 DS2483 single-channel 1-wire master with adjustable timing and sleep mode 1-wire triplet table 9. bit allocation in the direction byte x = dont care command code 78h command parameter direction byte description generates three time slots: two read time slots and one write time slot at the 1-wire line. the type of write time slot depends on the result of the read time slots and the direction byte. the direction byte determines the type of write time slot if both read time slots are 0 (a typi - cal case). in this case, the DS2483 generates a write-one time slot if v = 1 and a write-zero time slot if v = 0. see table 9. if the read time slots are 0 and 1, they are followed by a write-zero time slot. if the read time slots are 1 and 0, they are followed by a write-one time slot. if the read time slots are both 1 (error case), the subsequent write time slot is a write-one. typical use to perform a 1-wire search rom sequence; a full sequence requires this command to be executed 64 times to identify and address one device. restriction 1-wire activity must have ended before the DS2483 can process this command. error response command code and direction byte is not acknowledged if 1wb = 1 at the time the com - mand code is received and the command is ignored. command duration 3 x t slot + maximum 262.5ns, counted from the falling scl edge of the first bit (msb) of the direction byte. 1-wire activity begins maximum 262.5ns after the falling scl edge of the msb of the direction byte. read pointer position status register (for busy polling). status bits affected 1wb (set to 1 for 3 x t slot ), sbr is updated at the first t msr , tsb and dir are updated at the second t msr (i.e., at t slot + t msr ). device configurations affected 1ws, apu apply. port configurations affected t rstl , t msp , t w0l , t rec0 , and r wpu current values apply. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v x x x x x x x www.datasheet.co.kr datasheet pdf - http://www..net/ ???????????????????????????????????????????????????????????????? maxim integrated products 19 DS2483 single-channel 1-wire master with adjustable timing and sleep mode i 2 c interface general characteristics the i 2 c bus uses a data line (sda) and a clock signal (scl) for communication. both sda and scl are bidi - rectional lines connected to a positive supply voltage through a pullup resistor. when there is no communica - tion, both lines are high. the output stages of devices connected to the bus must have an open drain or open collector to perform the wired-and function. data on the i 2 c bus can be transferred at rates of up to 100kbps in standard mode and up to 400kbps in fast mode. the DS2483 works in both modes. a device that sends data on the bus is defined as a transmitter, and a device receiving data is defined as a receiver. the device that controls the communication is called a master. the devices that are controlled by the master are slaves. to be individually accessed, each device must have a slave address that does not conflict with other devices on the bus. data transfers can be initiated only when the bus is not busy. the master generates the serial clock (scl), con - trols the bus access, generates the start and stop conditions, and determines the number of data bytes transferred between start and stop ( figure 7 ). data is transferred in bytes with the most significant bit being transmitted first. after each byte follows an acknowledge bit to allow synchronization between master and slave. slave address figure 8 shows the slave address to which the DS2483 responds. the upper 7 bits are programmed at the fac - tory. contact the factory for a customized version with a different address. the slave address is part of the slave address/control byte. the last bit of the slave address/ control byte (r/ w ) defines the data direction. when set to 0, subsequent data flows from master to slave (write access mode); when set to 1, data flows from slave to master (read access mode). figure 7. i 2 c protocol overview figure 8. DS2483 slave address sda scl idle 1C7 8 9 1C7 8 9 1C 7 8 9 start condition stop condition repeated start slave address r/w ack ack data ack/ nack data msb first msb lsb msb lsb repeated if more bytes are transferred 0 a6 msb 0 a5 1 a4 1 a3 7-bit slave address 0 a2 0 a1 0 a0 r/w determines read or write www.datasheet.co.kr datasheet pdf - http://www..net/ ???????????????????????????????????????????????????????????????? maxim integrated products 20 DS2483 single-channel 1-wire master with adjustable timing and sleep mode i 2 c definitions the following terminology is commonly used to describe i 2 c data transfers. see figure 9 for a timing diagram. bus idle or not busy: both sda and scl are inac - tive and in their logic-high states. start condition: to initiate communication with a slave, the master must generate a start condition. a start condition is defined as a change in state of sda from high to low while scl remains high. stop condition: to end communication with a slave, the master must generate a stop condition. a stop condition is defined as a change in state of sda from low to high while scl remains high. repeated start condition: repeated starts are commonly used for read accesses to select a specific data source or address from which to read. the mas - ter can use a repeated start condition at the end of a data transfer to immediately initiate a new data transfer following the current one. a repeated start condition is generated the same way as a normal start condition, but without leaving the bus idle after a stop condition. data valid: with the exception of the start and stop condition, transitions of sda can occur only during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl plus the required setup and hold time (t hd:dat after the falling edge of scl and t su:dat before the rising edge of scl; see figure 9 ). there is one clock pulse per bit of data. data is shifted into the receiving device during the rising edge of scl pulse. when finished with writing, the master must release the sda line for a sufficient amount of setup time (minimum t su:dat + t r in figure 9 ) before the next ris - ing edge of scl to start reading. the slave shifts out each data bit on sda at the falling edge of the previ - ous scl pulse and the data bit is valid at the rising edge of the current scl pulse. the master generates all scl clock pulses, including those needed to read from a slave. acknowledge: typically a receiving device, when addressed, is obliged to generate an acknowledge after the receipt of each byte. the master must generate a clock pulse that is associated with this acknowledge bit. a device that acknowledges must pull sda low during the acknowledge clock pulse in such a way that sda is stable low during the high period of the acknowledge-related clock pulse plus the required setup and hold time (t hd:dat after the falling edge of scl and t su:dat before the rising edge of scl). figure 9. i 2 c timing diagram scl note: timing is referenced to v il(max) and v ih(min) . sda stop start repeated start spike suppression t buf t hd:sta t hd:dat t su:dat t su:sto t hd:sta t sp t su:sta t high t r t f t low www.datasheet.co.kr datasheet pdf - http://www..net/ ???????????????????????????????????????????????????????????????? maxim integrated products 21 DS2483 single-channel 1-wire master with adjustable timing and sleep mode not acknowledged by slave: a slave device could be unable to receive or transmit data, e.g., because it is busy performing a real-time function or is in sleep mode. in this case, the slave device does not acknowledge its slave address and leaves the sda line high. a slave device that is ready to communicate acknowledges at least its slave address. however, some time later the slave can refuse to accept data, e.g., because of an invalid command or parameter. in this case, the slave device does not acknowledge any of the bytes that it refuses and leaves sda high. in either case, after a slave has failed to acknowledge, the master first should generate a repeated start condition or a stop condition followed by a start condition to begin a new data transfer. not acknowledged by master: at some time when receiving data, the master must signal an end of data to the slave device. to achieve this, the master does not acknowledge the last byte that it has received from the slave. in response, the slave releases sda, allowing the master to generate the stop condition. writing to the DS2483 to write to the DS2483, the master must access the device in write mode, i.e., the slave address must be sent with the direction bit set to 0. the next byte to be sent is a command code, which, depending on the command, may be followed by a command parameter. the DS2483 acknowledges valid command codes and expected/ valid command parameters. additional bytes or invalid command parameters are never acknowledged. reading from the DS2483 to read from the DS2483, the master must access the device in read mode, i.e., the slave address must be sent with the direction bit set to 1. the read pointer determines the register that the master reads from. the master can continue reading the same register over and over again, without having to readdress the device, e.g., to watch the 1wb changing from 1 to 0. to read from a different register, the master must issue the set read pointer com - mand and then access the DS2483 again in read mode. i 2 c communication examples see table 10 and table 11 for the i 2 c communication legend and data direction codes. table 10. i 2 c communicationlegend table 11. data direction codes symbol description s start condition ad, 0 select DS2483 for write access ad, 1 select DS2483 for read access sr repeated start condition p stop condition a acknowledged a\ not acknowledged (idle) bus not busy ???????????????????????????????????????????????????????????????? maxim integrated products 22 DS2483 single-channel 1-wire master with adjustable timing and sleep mode i 2 c communication examples (continued) device reset (after power-up) s ad,0 a drst a sr ad,1 a ???????????????????????????????????????????????????????????????? maxim integrated products 23 DS2483 single-channel 1-wire master with adjustable timing and sleep mode i 2 c communication examples (continued) verifying the 1-wire port configuration the adjust 1-wire port command sets the read pointer to the port configuration register. if other commands were issued to the DS2483 since then, use the set read pointer command first to position the read pointer to the port configuration register. condition: 1-wire idle (1wb = 0), read pointer at port configuration register repeat to read additional port parameters s ad,1 a ???????????????????????????????????????????????????????????????? maxim integrated products 24 DS2483 single-channel 1-wire master with adjustable timing and sleep mode i 2 c communication examples (continued) 1-wire single bit (to generate a single time slot on the 1-wire line) case a: 1-wire idle (1wb = 0), no busy polling s ad,0 a 1wsb a a ???????????????????????????????????????????????????????????????? maxim integrated products 25 DS2483 single-channel 1-wire master with adjustable timing and sleep mode i 2 c communication examples (continued) 1-wire read byte (to read a byte from the 1-wire line) case a: 1-wire idle (1wb = 0), no busy polling, set read pointer after idle time s ad,0 a 1wrb a p (idle) s ad,0 a srp ad,1 a ???????????????????????????????????????????????????????????????? maxim integrated products 26 DS2483 single-channel 1-wire master with adjustable timing and sleep mode i 2 c communication examples (continued) 1-wire triplet (to perform a search rom function on 1-wire line) case a: 1-wire idle (1wb = 0), no busy polling s ad,0 a 1wt a ???????????????????????????????????????????????????????????????? maxim integrated products 27 DS2483 single-channel 1-wire master with adjustable timing and sleep mode applications information sda and scl pullup resistors sda is an open-drain output on the DS2483 that requires a pullup resistor to realize high-logic levels. because the DS2483 uses scl only as input (no clock stretching), the master can drive scl either through an open-drain/col - lector output with a pullup resistor or a push-pull output. pullup resistor r p sizing according to the i 2 c specification, a slave device must be able to sink at least 3ma at a v ol of 0.4v. this dc condition determines the minimum value of the pullup resistor: r p(min) = (v ci2c - 0.4v)/3ma . with an i 2 c pul - lup voltage v ci2c of 5.5v, the minimum value for the pul - lup resistor is 1.7k i . the minimum r p line in figure 10 shows how the minimum pullup resistor changes with the operating (pullup) voltage. for i 2 c systems, the rise time and fall time are measured from 30% to 70% of the pullup voltage. the maximum bus capacitance, c b , is 400pf. the maximum rise time must not exceed 300ns. assuming maximum rise time, the maximum resistor value at any given capacitance c b is calculated as: r p(max) = 300ns/(c b x ln(7/3)) . for a bus capacitance of 400pf, the maximum pullup resistor would be 885 i . because an 885 i pullup resistor, as would be required to meet the rise time specification at 400pf bus capaci - tance, is lower than r p(min) at 5.5v, a different approach is necessary. the maximum load at minimum r p fast mode line in figure 10 is generated by first calculating the minimum pullup resistor at any given operating volt - age (minimum r p line) and then calculating the respec - tive bus capacitance that yields a 300ns rise time. only for pullup voltages of 3v and lower can the maxi - mum permissible 400pf bus capacitance be maintained. a reduced 300pf bus capacitance is acceptable for 4v and lower pullup voltages. for fast mode operation at any pullup voltage, the bus capacitance must not exceed 200pf. the corresponding pullup resistor value at the voltage is indicated by the minimum r p line. figure 10. i 2 c fast mode pullup resistor selection chart minimum r p maximum load at minimum r p fast mode 2000 minimum r p ( ) load (pf) pullup voltage (v) 1600 1200 800 400 1 2 3 4 5 0 500 400 300 200 100 0 www.datasheet.co.kr datasheet pdf - http://www..net/ ???????????????????????????????????????????????????????????????? maxim integrated products 28 DS2483 single-channel 1-wire master with adjustable timing and sleep mode ordering information package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. + denotes a lead(pb)-free/rohs-compliant package. t = tape and reel. * ep = exposed pad. part temp range pin-package DS2483r+t -40 n c to +85 n c 6 sot23 (3k pieces) DS2483q+t -40 n c to +85 n c 8 tdfn-ep* (2.5k pieces) package type package code outline no. land pattern no. 6 sot23 u6sn+1 21-0058 90-0175 8 tdfn-ep t823+1 21-0174 90-0091 www.datasheet.co.kr datasheet pdf - http://www..net/ maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 29 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. DS2483 single-channel 1-wire master with adjustable timing and sleep mode revision history revision number revision date description pages changed 0 12/11 initial release www.datasheet.co.kr datasheet pdf - http://www..net/ |
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